In a conventional pipelined analog-to-digital converter (ADC), as illustrated in FIG. 1, each stage e.g. 110 typically has one flash ADC e.g. 102 and one MDAC e.g. 104. The output of the flash ADC 102 is a thermometric code, which is converted to a digital code by some digital logic, e.g. circuits 108, 118. The digital code (e.g. a binary code) is then used to select the reference signal for the MDAC 104. The analog output from the MDAC 104 is subtracted from the original input such that the residue portion of the original input is amplified and provided to the next stage e.g. 120, and so on, until all the bits are resolved. However, at high speeds, e.g. about 1 gigahertz (GHz), the delay in the digital logic consumes a major portion of the time in which the output of the MDAC 104 has to settle down. This delay increases the bandwidth requirement of the operational amplifier (op-amp) e.g. 106. It is noted that each pipelined stage typically also has another thermometric to binary code converter (not shown), which outputs the digital bits (e.g. for a 2.5 bit pipelined stage, 3 digital bits) for each stage. The digital bits from each stage then go to the digital error correction logic, and finally the overall digital bits of the ND converter are output.
There have been attempts to implement the pipelined ADC 100, in particular the MDAC 104 (FIG. 1).
FIG. 2 shows a schematic circuit diagram illustrating a conventional MDAC 200 for a 2.5-bit stage. Here, an input signal is sampled onto the bottom plates of four capacitors C1, C2, C3 and C4 of equal capacitance C in a first phase PH1. In a second phase PH2, capacitor C1 is coupled between input and output of the op-amp 206 as a feedback capacitor, and capacitors C2, C3, C4 are either coupled to non-inverting reference input REFP or inverting reference input REFM, or coupled via a low-resistance path to a common mode reference voltage, according to the output of the flash ADC (e.g. 102 in FIG. 1), e.g. using switches e.g. 202.
Output voltage Vres of the MDAC 200 can be given by the following equation:Vres=4*Vin−X*Vref  (1)where X=0, +/−1, +/−2, +/−3 (in binary form) is the input digital value after conversion from the thermometric code; Vin is the voltage level of non-inverting input INP and inverting input INM; Vref is the voltage level of non-inverting reference input REFP and inverting reference input REFM.
When X=0, the bottom plates of capacitors C2, C3, C4 are coupled to the common mode reference voltage, which uses an extra buffer to drive these capacitors. When X={+/−1, +/−2, +/−3}, capacitors C2, C3, C4 are coupled to either the non-inverting reference input REFP or inverting reference input REFM. Therefore, the amount of capacitance changes from cycle to cycle, thus requiring the reference voltage, which is changing, to settle with approximately full accuracy.